Generally speaking, computer systems typically include one or more central processor units (CPUs). Such CPUs typically include circuits for performing logical and arithmetic operations on data elements stored in main memory. Those circuits are designed such that each possible combination of data elements causes the assertion of only one selected output signal that is part of a group of output signals. In other words, such circuits produce outputs that are asserted in a mutually exclusive manner.
For example, when operands are added in a CPU's arithmetic logic circuit, the overall addition operation is performed as a series of smaller addition operations. Such an addition operation typically begins by adding a least significant portion of each operand using a first arithmetic or "adder" circuit. That adder circuit produces a sum value and a carry-out value. That sum value becomes the least significant portion of the overall sum value. The carry-out value is conveyed to a second adder circuit that adds it to a more significant portion of each operand to form another sum value and another carry-out value. Such intermediate addition operations are performed until all of the bits of the operands have been added together and the overall sum and carry-out value have been computed.
As is known in the art, the overall addition operation can be more quickly performed when the carry values are calculated in parallel. Such carry values are represented by mutually exclusive signals indicating what is to be done with that carry signal, rather than rippling the carry signal through each adder circuit. Such mutually exclusive signals are referred to as carry status signals and are utilized by carry lookahead adder circuits.
Carry status signals can represent three possible conditions that arise with respect to carry-out values. Those conditions are referred to as "generate", "kill" and "propagate" conditions. An adder circuit "generates" a carry-out value when it adds two operands that produce a resulting sum value having a component that is to be added to the next most significant operands. For example, consider a one bit adder than adds a logical "one" to another logical "one". The result is a sum value of zero and a carry out component of one. Such a carry out component is represented by the assertion of a "generate" carry status signal.
Second, when an adder circuit does not produce a carry-out value, it is referred to as having "killed" the carry value. For example, consider that the one bit adder adds a logical "zero" to another logical "zero". The result is a sum value of zero and a carry out component of zero. Such a carry out component is represented by the assertion of a "kill" carry status signal.
Lastly, where an adder circuit receives a carry-in value from a less significant adder circuit and the associated addition operation causes the creation of an identical carry-out value, the adder circuit is said to "propagate" the carry signal. For example, consider that the one bit adder adds a logical "one" to a logical "zero" and a logical "one" carry in value. The result is a sum value of zero and a carry out component of one. The carry out component is the same as the carry in value and therefore is referred to as being propagated.
Such mutually exclusive generate, kill and propagate signals are generated by each adder in parallel and are aggregated by a carry lookahead circuit to form an overall carry value for the entire addition operation.
In the prior art, circuits that produce such mutually exclusive output signals were difficult to implement because they were slow and/or required a large amount of semiconductor real estate. Such a result flows from the fact that such circuits were typically designed using either the full complementary CMOS logic family, the dynamic CMOS logic family, or the pseudo-NMOS logic family.
When the generate, kill and propagate signals are combined in a carry lookahead circuit implemented using the full complementary CMOS logic family, each of the input signals is connected to the gate terminals of both an NMOS transistor and a PMOS transistor. Accordingly, such an approach requires the implementation of a large number of PMOS transistors. PMOS transistors can significantly slow down the operation of a circuit since they have lower conductance and induce significant levels of parasitic capacitance. As such, logic families that require the use of a large number of PMOS transistors are not desired.
The standard dynamic CMOS logic family has also been used to implement such circuits. Circuits designed using the standard dynamic CMOS logic family couple the input signals only to NMOS transistors. The NMOS transistors can only pull internal signals of the circuit to logic low levels in response to an assertion of the input signal. Therefore, circuits designed using this logic family require a pre-charge device for returning them to logic high levels between evaluation operations. Pre-charge devices are implemented using PMOS transistors coupled to a Vdd voltage supply (Vdd). As such, the standard dynamic CMOS logic family allows logic circuits to be implemented using fewer PMOS transistors and therefore offers potential speed and area advantages over the full complementary CMOS logic family. However, such a logic family has a higher power consumption, is more susceptible to electrical disturbances and restricts the behavior of input signals. Consequently, dynamic logic is often undesirable.
Further, the pseudo-NMOS logic family requires that input signals are connected only to NMOS transistors that form conductive paths to electrical ground (Vss). Associated paths to Vdd are provided by relatively weak PMOS transistors, each having a gate terminal coupled to Vss. Accordingly, circuit paths are only weakly pulled up to logic high levels such that they can be pulled down by an associated NMOS transistor that has been turned-on.
Implementation of a circuit using the pseudo-NMOS logic family allows fewer transistors to be implemented, thereby reducing the amount of semiconductor real-estate that is used. However, such circuit implementations typically consume significant amounts of power. That power drain is due to the fact that when the NMOS transistors are turned-on, a path is generated that allows current to flow from Vdd to Vss. While such a power drain may not be significant with regards to a single circuit, such design methodologies are typically used to design many replicated versions of the same circuit. Accordingly, this logic family is not desired due to its significant power consumption characteristics.
Therefore, the logic families used in the prior art present undesirable tradeoffs of speed, semiconductor area and power consumption that have to be weighed before a circuit is implemented.